ULEIS Level 1 Data Structures



uleis_dump.h , v 1.6


#include "hdfi.h"

#define U_DUMP_SIZE    125	/* Memory dump size in bytes */

struct UDumpSet
{
  uint32 output_sctime;		/* time for beginning of data output cycle */
  uint32 collect_sctime;	/* time for beginning of data collection */
  uint32 QAC;			/* number of bad frames in this cycle */

  uint16 dumptime_offset;	/* offset for output_sctime for dump */
  uint8 dump[U_DUMP_SIZE];      /* dump: 125 bytes */

};

uleis_evnt.h , v 1.8


#include "hdfi.h"

#define U_BYT_EVNT_SIZE    21		/* 21 bytes per event */
#define U_EVNT_NUM         14		/* number of 12 bit events */
#define U_EVTSECTR          6 		/* 6 events per sector */
#define U_SECTRS            8		/* 8 sectors, 0-7 */
#define U_SPINS            10 		/* 10 spins, 1-10 */
 

struct UEvntSet
{
  uint32 output_sctime;		/* time for beginning of data output cycle */
  uint32 collect_sctime;	/* time for beginning of data collection */
  uint32 QAC;			/* number of bad frames in this cycle */

   /* Events: 10 spins, 8 sectors, 6 events, event num (14) */
  uint16 event[U_SPINS][U_SECTRS][U_EVTSECTR][U_EVNT_NUM];
};

uleis_hskp.h , v 1.8


#include "hdfi.h"

#define NUMFRM 128		/* number of minor frames in a cycle */

struct UHskpSet
{
  uint32 output_sctime;		/* time for beginning of data output cycle */
  uint32 collect_sctime;	/* time for beginning of data collection */

  uint32 QAC;			/* number of missing frames in this cycle */
  uint8 chk_sum_chk;	      /* 0 means chk_sum test passed; 1 means failed */
                              /*   also in uleis_statblk_trl.h               */

   /* position flag (1 = yes, 0 = no) of dump data in each mnr frm */
   /* puts the total for this minor frame in last array element */
  uint8 dump_flg[129];

   /* position flag (1 = yes, 0 = no) of Status TLM data in each mnr frm */
   /* puts the total for this minor frame in last array element */
  uint8 stat_tlm_flg[129];

  uint8 DeckTemp[8];		/* mf 0  - Instrument Deck Temp: near ULEIS */
  uint8 lvps_voltage[8];	/* mf 9  - lvps voltage */
  uint8 total_cur[8];		/* mf 10 - total current */
  uint8 lvps_cur_analg[8];	/* mf 10 - analog elect. lvps current */
  uint8 heater_cur[8];		/* mf 10 - Internal & I/F Heater Current */
  uint8 telescp_temp[8];	/* mf 12 - telescope temperature */
  uint8 analg_elect_temp[8];	/* mf 12 - analog electr. temp. (internal) */
  uint8 dpu_temp[8];		/* mf 12 - dpu temperature (internal) */

  uint8 UPowBits[8];		/* power switching and ordinance array */
/*- ULEIS power switching and ordinance (start bit count at 1, not 0) -*/
/*  element postn 7: Internal Heaters         bit pos 20 of 112 (ON/OFF) */
/*  element postn 6: Interface Heater         bit pos 21 of 112 (ON/OFF) */
/*  element postn 5: Main System Power        bit pos 24 of 112 (ON/OFF) */
/*  element postn 4: Pyro A Arm (ICI-1SE192F) bit pos 60 of 112 (ON/OFF) */
/*  element postn 3: Pyro B Arm (ICI-1SE192F) bit pos 63 of 112 (ON/OFF) */
/*  element postn 2: 0                                                   */
/*  element postn 1: 0                                                   */
/*  element postn 0: 0                                                   */

  /* sunpulse data */
  uint8  PhaseAng[NUMFRM];   /* Phase angle for each frame in this cycle*/
  uint8  SunSenID[NUMFRM];   /* bits 7-2=0, bit1=sunsentop,bit0=sunsenside*/
  uint16 SunPulLat[2][8];     /* sun pulse latched at mn frm 0&8 [2] */
			     /* over the 8 [8] major frame cycle */
			     /* SC spin clock value at the time of the sun */
			     /* pulse */
  uint32 SunPulDat[2][8];    /* Time of sun pulse */
		/* bits 31-24 : unused */
		/* bits 23-20 : Mnr frame */
		/* bits 19-10 : sub secont count (684.75 cnts=1 sec)*/
		/* bits  9- 8 : ID bits, 00=err,01=top,10=side,11=neither */
		/* bits  7- 0 : Y angle measurment (Grey code) */
		/* */
		/*   From C&DH Specification (mf0:index1=0, mf8:index1=1) */
		/* For the time tag in Science minor frame 0: for a minor */
		/* frame ID of 0, the sun pulse would have occured in the */
		/* current major frame.  For a minor frame ID of 1 to 15, */
		/* the sun pulse would have occured in the previous major */
		/* frame */
		/* For the time tag in Science minor frame 8: for a minor */
		/* frame ID of 0-8, the sun pulse would have occured in the */
		/* current major frame.  For a minor frame ID of 9 to 15, */
		/* the sun pulse would have occured in the previous major */
		/* frame */


};

uleis_rate.h , v 1.5


#include "hdfi.h"

#define U_SPINS               10 	/* 10 spins, 1-10 */
#define U_SPINPRS              5	/* 5 spin pairs 1-5 */
#define U_SECTRS               8	/* 8 sectors, 0-7 */
#define U_MTRX_RATE_SIZE      34	/* 34 bytes per sector */
#define U_MTRX_PRS_RATE_SIZE  42	/* 42 bytes per sector */
#define U_SNGL_RATE_SIZE      16        /* 16 2-byte items per sector */

struct URateSet
{
  uint32 output_sctime;		/* time for beginning of data output cycle */
  uint32 collect_sctime;	/* time for beginning of data collection */
  uint32 QAC;			/* number of bad frames in this cycle */

  /* Matrix rates: 34 bytes, 10 spins, 8 sectors */
  uint8 Matrx[U_MTRX_RATE_SIZE][U_SPINS][U_SECTRS];

  /* Matrix pair rates: 42 bytes, 5 spin pairs, 8 sectors */
  uint8 Matrx_prs[U_MTRX_PRS_RATE_SIZE][U_SPINPRS][U_SECTRS];

  /* Singles rates:  32 bytes, 5 spin pairs, 8 sectors */
  uint16 Single[U_SNGL_RATE_SIZE][U_SPINPRS][U_SECTRS];
};


uleis_stat_tlm.h , v 1.5


#include "hdfi.h"

#define U_STAT_TLM_SIZE    125		/* Status TLM length 125 bytes */

struct UStatTLMSet
{

  uint32 output_sctime;		/* time for beginning of data output cycle */
  uint32 collect_sctime;	/* time for beginning of data collection */
  uint32 QAC;			/* number of bad frames in this cycle */

  uint16 stattlmtime_offset;	/* offset for output_sctime for Status TLM */

     /* Status TLM: 125 bytes */
  uint8  StatusTLM[U_STAT_TLM_SIZE];

};

uleis_statblk_trl.h , v 1.8


#include "hdfi.h"

#define U_MAJFRM              8		/* 8 major frames (0-7) */
#define U_STATBLK_SIZE       14		/* Status block of 14 bytes */
#define U_TRL_SIZE           128	/* Status trailer of 128 bytes */

struct UStatBlkTrlSet
{
  uint32 output_sctime;		/* time for beginning of data output cycle */
  uint32 collect_sctime;	/* time for beginning of data collection */
  uint32 QAC;			/* number of bad frames in this cycle */
  uint8 chk_sum_chk;	      /* 0 means chk_sum test passed; 1 means failed */
                              /*   also in uleis_hskp.h                      */

     /* Status Block: 8 major frames, 14 bytes */
/*  uint8 statblock[U_MAJFRM][U_STATBLK_SIZE];*/

     /* Status Trailer: 128 bytes */
/*  uint8 trailer[U_TRL_SIZE];*/


/* variable set */

     /* Status Block: 112 bytes */
  uint16 Sync;               /*Status Block 0   Byte  1- 2 */ /* = FAFE */ 
  uint16 SoftwareID;                         /* Byte  3- 4 */
  uint16 MinFrCnt;                           /* Byte  5- 6 */
  uint16 CmdAccCnt;                          /* Byte  7- 8 */
  uint16 CmdRejCnt;                          /* Byte  9-10 */
  uint32 CmdEcho;                            /* Byte 11-14 */
  uint32 RejCmdEcho;         /*Status Block 1   Byte  1- 4 */
  uint16 CmdSide1IntrCnt;                    /* Byte  5- 6 */
  uint16 CmdSide2IntrCnt;                    /* Byte  7- 8 */
  uint16 CodePagNum;                         /* Byte  9-10 */
  uint16 SunSectrID;                         /* Byte 11-12 */
  uint16 SpinCntReg;                         /* Byte 13-14 */
  uint16 WatchdogCnt;        /*Status Block 2   Byte  1- 2 */
  uint16 RamPag1TestRslts;                   /* Byte  3- 4 */
  uint16 RamPag2TestRslts;                   /* Byte  5- 6 */
  uint16 EEPROMCksum;                        /* Byte  7- 8 */
  uint16 TimerIntrCnt;                       /* Byte  9-10 */
  uint16 CurTLMSide;                         /* Byte 11-12 */
  uint16 DefTLMSide;                         /* Byte 13-14 */
  uint16 MemPekVal;          /*Status Block 3   Byte  1- 2 */
  uint16 MemPekPagNum;                       /* Byte  3- 4 */
  uint16 MemPekAddr;                         /* Byte  5- 6 */
  uint16 MemPokVal;                          /* Byte  7- 8 */
  uint16 MemPokPagNum;                       /* Byte  9-10 */
  uint16 MemPokAddr;                         /* Byte 11-12 */
  uint16 MemDmpPagNum;                       /* Byte 13-14 */
  uint16 MemDmpAddrPntr;     /*Status Block 4   Byte  1- 2 */
  uint16 OutputPort0PokVal;                  /* Byte  3- 4 */
  uint16 OutputPort1PokVal;                  /* Byte  5- 6 */
  uint16 OutputPort2PokVal;                  /* Byte  7- 8 */
  uint16 OutputPort6PokVal;                  /* Byte  9-10 */
  uint16 InputPort0Val;                      /* Byte 11-12 */
  uint16 InputPort1Val;                      /* Byte 13-14 */
  uint16 InputPort2Val;      /*Status Block 5   Byte  1- 2 */
  uint16 InputPort6Val;                      /* Byte  3- 4 */
  uint16 EEPROMPag3Stat;                     /* Byte  5- 6 */
  uint16 EEPROMPag67Stat;                    /* Byte  7- 8 */
  uint16 CtrlWord2CmdStat;                   /* Byte  9-10 */
  uint16 MemLdSiz;                           /* Byte 11-12 */
  uint16 MemLdPag;                           /* Byte 13-14 */
  uint16 MemLdAddr;          /*Status Block 6   Byte  1- 2 */
  uint16 MemLdCksum;                         /* Byte  3- 4 */
  uint16 MemLdComCksum;                      /* Byte  5- 6 */
  uint16 MemLdCksumErrCnt;                   /* Byte  7- 8 */
  uint16 AECmdErrCnt;                        /* Byte  9-10 */
  uint16 AECmdIntrCnt;                       /* Byte 11-12 */
  uint16 MajFrCntx8;                         /* Byte 13-14 */
  uint16 Spn1SpnCnt;         /*Status Block 7   Byte  1- 2 */
  uint16 Spn2SpnCnt;                         /* Byte  3- 4 */
  uint16 Spn3SpnCnt;                         /* Byte  5- 6 */
  uint16 Spn4SpnCnt;                         /* Byte  7- 8 */
  uint16 Spn5SpnCnt;                         /* Byte  9-10 */
  uint16 Spn6SpnCnt;                         /* Byte 11-12 */
  uint16 Spn7SpnCnt;                         /* Byte 13-14 */

     /* Status Trailer: 128 bytes 	(as of 4/7/97) */
  uint16 Spn8SpnCnt;        /*Status Trailer   Byte   1-  2 */
  uint16 Spn9SpnCnt;                        /* Byte   3-  4 */
  uint16 Spn10SpnCnt;                       /* Byte   5-  6 */
  uint16 CumSpnCnt;                         /* Byte   7-  8 */
  uint16 EvntCnt;                           /* Byte   9- 10 */
  uint16 Spn1MinFrCnt;                      /* Byte  11- 12 */
  uint8  HVAutFlg;                          /* Byte  13     */
  uint8  HVActFlg;                          /* Byte  14     */

  uint8  HK_ADC[16][3];                     /* Byte  15- 62 */

  uint8  PHAFrzFlg;			    /* Byte  63     0=dsabl,1=enbl*/
  uint8  SSDEnaFlg;                         /* Byte  64     */
  uint8  AEAutoResetEnaFlg;                 /* Byte  65     */
  uint8  CalModFlg;                         /* Byte  66     */
  uint8  TOFFlg;                            /* Byte  67     22=TOF1,24=TOF2*/
  uint8  AETlltlBits;                       /* Byte  68     */
  uint16 MotrAutFlg;                        /* Byte  69- 70 */
  uint8  MotrPwrFlg;                        /* Byte  71     0=off,nonzero=on*/
  uint8  MotrFid;                           /* Byte  72     */
  uint16 MotrPostn;                         /* Byte  73- 74 */


  uint16 Rt1MinSectr;                       /* Byte  75- 76 */
  uint16 Rt1MinSpn;                         /* Byte  77- 78 */
  uint16 Rt1HiSecErrLim;                    /* Byte  79- 80 */
  uint16 Rt1LoSecErrLim;                    /* Byte  81- 82 */
  uint16 Rt1HiSpnErrLim;                    /* Byte  83- 84 */
  uint16 Rt1LoSpnErrLim;                    /* Byte  85- 86 */
  uint16 Rt1Indx;                           /* Byte  87- 88 */


  uint16 Rt2MinSectr;                       /* Byte 89-90   */
  uint16 Rt2MinSpn;                         /* Byte 91-92   */
  uint16 Rt2HiSecErrLim;                    /* Byte 93-94   */
  uint16 Rt2LoSecErrLim;                    /* Byte 95-96   */
  uint16 Rt2HiSpnErrLim;                    /* Byte 97-98   */
  uint16 Rt2LoSpnErrLim;                    /* Byte 99-100  */
  uint16 Rt2Indx;                           /* Byte 101-102 */
  uint16 MtrErrFlg;                         /* Byte 103-104 */
  uint8  MtrMotnFlg;                        /* Byte 105     0=No Motion*/
  uint8  EvntRdoutFmt;                      /* Byte 106     */
  uint8  MUXSelMd;                          /* Byte 107     */
  uint8  VS1Enab;                           /* Byte 108     */
  uint8  VS2Enab;                           /* Byte 109     */
  uint8  VS1VS2Enab;                        /* Byte 110     */
  uint16 PHARnkSpn1Sec1;                    /* Byte 111-112 */
  uint16 PHARnkSpn1Sec2;                    /* Byte 113-114 */
  uint16 PHARnkSpn1Sec3;                    /* Byte 115-116 */
  uint16 PHARnkSpn1Sec4;                    /* Byte 117-118 */
  uint16 PHARnkSpn1Sec5;                    /* Byte 119-120 */
  uint16 PHARnkSpn1Sec6;                    /* Byte 121-122 */
  uint16 PHARnkSpn1Sec7;                    /* Byte 123-124 */
  uint16 PHARnkSpn1Sec8;                    /* Byte 125-126 */
  /* 16-bit sum of first 7999 words */
  uint16 SciRecCksum;                       /* Byte 127-128 */

}; 

uleis_br_db.h , v 1.2

/* The variables and arrays below are assigned values from the files */
/* in the ~asc/aceprog/uleis_br_db directory */

#include "hdfi.h"

struct UleisDB
{
  float64 begin_time_in_sec; /* seconds since Jan 1 1970 */
  float64 end_time_in_sec;  /* seconds since Jan 1 1970 */

/*H,H, 3He, 4He,4He, O,O, Fe,Fe by Rate_assignment, Detectors, Efficiency(Avg)*/
  float64 species[9][3];

/*ULEIS Detector Geometry Factors vs. Iris settings (i.e. motor position)*/
/* D1, D2, D3, D4, D5, D6, D7 by Iris settings of: 100%, 25%, 6%, 1% */
  float64 detector[7][4];

};

uleis_br_out.h , v 1.2

#include "hdfi.h"

struct Uleis_br_out
{
  float64 bin_start;  /* beginning of bin. # of sec since Jan 1 1996 UTC */
  float64 bin_end;    /* end of bin. # of sec since Jan 1 1996 UTC */

  float32 ULEIS_livetime;   /* livetime for this measurement. */

  uint16 rate_assign[9];
  float32 brws_rates[9];
};

For comments, questions or suggestions regarding these data structures,
email: asc@srl.caltech.edu
Last update: Wed Nov 3 12:45:33 PST 1999